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19-0155; Rev 2; 1/96
Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs
_______________General Description
The MAX509/MAX510 are quad, serial-input, 8-bit voltage-output digital-to-analog converters (DACs). They operate with a single +5V supply or dual 5V supplies. Internal, precision buffers swing rail-to-rail. The reference input range includes both supply rails. The MAX509 has four separate reference inputs, allowing each DAC's full-scale range to be set independently. 20-pin DIP, SSOP, and SO packages are available. The MAX510 is identical to the MAX509 except it has two reference inputs, each shared by two DACs. The MAX510 is housed in space-saving 16-pin DIP and SO packages. The serial interface is double-buffered: A 12-bit input shift register is followed by four 8-bit buffer registers and four 8-bit DAC registers. A 12-bit serial word is used to load data into each register. Both input and DAC registers can be updated independently or simultaneously with single software commands. Two additional asynchronous control pins provide simultaneous updating (LDAC) or clearing (CLR) of input and DAC registers. The interface is compatible with MicrowireTM and SPI/ QSPITM. All digital inputs and outputs are TTL/CMOS compatible. A buffered data output provides for readback or daisy-chaining of serial devices.
____________________________Features
o o o o o Single +5V or Dual 5V Supply Operation Output Buffer Amplifiers Swing Rail-to-Rail Reference Input Range Includes Both Supply Rails Calibrated Offset, Gain, and Linearity (1LSB TUE) 10MHz Serial Interface, Compatible with SPI, QSPI (CPOL = CPHA = 0) and Microwire o Double-Buffered Registers for Synchronous Updating o Serial Data Output for Daisy-Chaining o Power-On Reset Clears Serial Interface and Sets All Registers to Zero
MAX509/MAX510
______________Ordering Information
PART MAX509ACPP MAX509BCPP MAX509ACWP MAX509BCWP MAX509ACAP MAX509BCAP MAX509BC/D TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 20 Plastic DIP 20 Plastic DIP 20 Wide SO 20 Wide SO 20 SSOP 20 SSOP Dice* TUE (LSB) 1 1 1/2 1 1 1/2 1 1 1/2 1 1/2
_______________Functional Diagrams
CLR DOUT LDAC AGND DGND VSS VDD REFB DECODE CONTROL REFA
Ordering Information continued on last page. * Dice are specified at +25C, DC parameters only. **Contact factory for availability and processing to MIL-STD-883.
_________________Pin Configurations
OUTA
MAX509
TOP VIEW
OUTB 1 OUTA 2 OUTB 20 OUTC 19 OUTD 18 V DD INPUT REG A DAC REG A DAC A
12-BIT SHIFT REGISTER
INPUT REG B
DAC REG B
DAC B
V SS 3 REFB 4
MAX509
17 REFC 16 REFD 15 CS 14 N.C. 13 SCLK 12 DIN 11 CLR
OUTC INPUT REG C DAC REG C DAC C
REFA 5 AGND 6 N.C. 7
OUTD SR CONTROL INPUT REG D DAC REG D DAC D
DGND 8 LDAC 9 DOUT 10
CS DIN SCLK
REFC
REFD
Functional Diagrams continued at end of data sheet.
DIP/SO/SSOP Pin Configurations continued at end of data sheet.
Microwire is a trademark of National Semiconductor. SPI and QSPI are trademarks of Motorola.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510
ABSOLUTE MAXIMUM RATINGS
VDD to DGND ..............................................................-0.3V, +6V VDD to AGND...............................................................-0.3V, +6V VSS to DGND ...............................................................-6V, +0.3V VSS to AGND ...............................................................-6V, +0.3V VDD to VSS .................................................................-0.3V, +12V Digital Input Voltage to DGND ......................-0.3V, (VDD + 0.3V) REF_....................................................(VSS - 0.3V), (VDD + 0.3V) OUT_..............................................................................VDD, VSS Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 16-Pin Plastic DIP (derate 10.53mW/C above +70C) ....842mW 16-Pin Wide SO (derate 9.52mW/C above +70C) .........762mW 16-Pin CERDIP (derate 10.00mW/C above +70C) ........800mW 20-Pin Plastic DIP (derate 11.11mW/C above +70C)....889mW 20-Pin Wide SO (derate 10.00mW/C above +70C) .......800mW 20-Pin SSOP (derate 10.00mW/C above +70C) ............800mW 20-Pin CERDIP (derate 11.11mW/C above +70C) ........889mW Operating Temperature Ranges: MAX5_ _ _C_ _ .....................................................0C to +70C MAX5_ _ _E_ _ ..................................................-40C to +85C MAX5_ _ _MJ_ ................................................-55C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Note: The outputs may be shorted to VDD, VSS, or AGND if the package power dissipation is not exceeded. Typical short-circuit current to AGND is 50mA. Do not bias AGND more than +1V above DGND, or more than 2.5V below DGND.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V 10%, VSS = 0V to -5.5V, VREF = 4V, AGND = DGND = 0V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER STATIC ACCURACY Resolution VREF = +4V, VSS = 0V or -5V 10% VREF = -4V, VSS = -5V 10% Guaranteed monotonic Code = 00 hex, VSS = 0V Zero-Code Error ZCE Code = 00 hex, VSS = -5V 10% Zero-Code-Error Supply Rejection Zero-Code Temperature Coefficient Full-Scale Error Full-Scale-Error Supply Rejection Full-Scale-Error Temperature Coefficient MAX5_ _C MAX5_ _E MAX5_ _M MAX5_ _C MAX5_ _E MAX5_ _M 1 10 14 MAX5_ _C MAX5_ _E MAX5_ _M 1 1 1 10 4 8 12 V/C mV MAX5_ _A MAX5_ _B MAX5_ _A MAX5_ _B 8 1 1.5 1 1.5 1 14 16 20 14 16 20 2 mV V/C mV mV LSB LSB Bits SYMBOL CONDITIONS MIN TYP MAX UNITS
Total Unadjusted Error
TUE
Differential Nonlinearity
DNL
Code = 00 hex, VDD = 5V 10%, VSS = 0V or -5V 10% Code = 00 hex Code = FF hex Code = FF hex, VDD = +5V 10%, VSS = 0V or -5V 10% Code = FF hex
2
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Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 10%, VSS = 0V to -5.5V, VREF = 4V, AGND = DGND = 0V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER REFERENCE INPUTS Input Voltage Range Input Resistance (Note 1) Input Capacitance (Note 2) Channel-to-Channel Isolation AC Feedthrough DAC OUTPUTS Full-Scale Output Voltage VREF = 4V, load regulation 1/4LSB VREF = -4V, VSS = -5V 10%, load regulation 1/4LSB Resistive Load VREF = VDD MAX5_ _C/E, load regulation 1LSB VREF = VDD MAX5_ _M, load regulation 2LSB DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage DYNAMIC PERFORMANCE MAX5_ _C Voltage-Output Slew Rate Output Settling Time (Note 6) Digital Feedthrough Digital-to-Analog Glitch Impulse Signal-to-Noise + Distortion Ratio Multiplying Bandwidth Wideband Amplifier Noise SINAD Positive and negative MAX5_ _E MAX5_ _M To 1/2LSB, 10k II 100pF load Code = 00 hex, all digital inputs from 0V to VDD Code 128127 VREF = 4Vp-p at 1kHz, VDD = 5V, code = FF hex VREF = 4Vp-p at 20kHz, VSS = -5V 10% VREF = 0.5Vp-p, 3dB bandwidth 1.0 0.7 0.5 6 5 12 87 74 1 60 MHz VRMS s nV-s nV-s dB V/s VOH VOL ISOURCE = 0.2mA ISINK = 1.6mA VDD - 0.5 0.4 V V VIH VIL IIN CIN VIN = 0V or VDD (Note 5) 2.4 0.8 1.0 10 V V A pF VSS 2 2 10 10 k VDD V Code = 55 hex Code = 00 hex (Note 3) (Note 4) MAX509 MAX510 MAX509 MAX510 VSS 16 8 24 12 15 30 -60 -70 VDD V k pF dB dB SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX509/MAX510
3
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Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 10%, VSS = 0V to -5.5V, VREF = 4V, AGND = DGND = 0V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER POWER SUPPLIES Positive Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current SYMBOL VDD VSS IDD ISS CONDITIONS For specified performance For specified performance Outputs unloaded, all digital inputs = 0V or VDD VSS = -5V 10%, outputs unloaded, all digital inputs = 0V or VDD MAX5_ _C/E MAX5_ _M MAX5_ _C/E MAX5_ _M MIN 4.5 -5.5 5 5 5 5 TYP MAX 5.5 0 10 12 10 12 UNITS V V mA mA
Note 1: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex. Note 2: Input capacitance is code dependent. The highest input capacitance occurs at code = 00 hex. Note 3: VREF = 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the code of all other DACs to 00 hex. Note 4: VREF = 4Vp-p, 10kHz. DAC code = 00 hex. Note 5: Guaranteed by design. Note 6: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.
TIMING CHARACTERISTICS
(VDD = +5V 10%, VSS = 0V to -5V, VREF = 4V, AGND = DGND = 0V, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER LDAC Pulse Width Low CS Rise to LDAC Fall Setup Time CLR Pulse Width Low SERIAL INTERFACE TIMING CS Fall to SCLK Setup Time SCLK Fall to CS Rise Hold Time SCLK Rise to CS Rise Hold Time SCLK Fall to CS Fall Hold Time DIN to SCLK Rise Setup Time DIN to SCLK Rise Hold Time SCLK Clock Frequency SCLK Pulse Width High SCLK Pulse Width Low SCLK to DOUT Valid tCSS tCSH2 tCSH1 tCSH0 tDS tDH fCLK tCH tCL tDO MAX5_ _C/E MAX5_ _M MAX5_ _C/E MAX5_ _M MAX5_ _C/E MAX5_ _M MAX5_ _C/E MAX5_ _M MAX5_ _C/E MAX5_ _M (Note 9) (Note 7) MAX5_ _C/E MAX5_ _M 40 50 0 40 0 40 50 0 20 20 40 50 40 50 10 10 12.5 10 ns ns ns ns ns ns MHz ns ns 100 100 ns SYMBOL tLDW tCLL tCLW MAX5_ _C/E MAX5_ _M (Notes 7, 8) MAX5_ _C/E MAX5_ _M CONDITIONS MIN 40 50 0 40 50 TYP 20 25 20 25 MAX UNITS ns ns ns
Note 7: Guaranteed by design. Note 8: If LDAC is activated prior to CS's rising edge, it must stay low for tLDW or longer after CS goes high. Note 9: Minimum delay from 12th clock cycle to CS rise. 4 _______________________________________________________________________________________
Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs
__________________________________________Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
OUTPUT SINK CURRENT vs. (VOUT - VSS)
MAX509-FG01
MAX509/MAX510
OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE
VDD = VREF = +5V VSS = GND DIGITAL INPUT = FF HEX
MAX509-FG10
SUPPLY CURRENT vs. TEMPERATURE
MAX509-FG02
12 10 8
-25 -20
7 6 SUPPLY CURRENT (mA) 5 4 3 2 1 VDD = +5.5V VSS = -5.5V VREF = -4.75 ALL DIGITAL INPUTS = +5V ISS IDD
IOUT (mA) VDD = VREF = +5V VSS = GND = 0V ALL DIGITAL INPUTS = 00 HEX 0 0.2 0.4 0.6 0.8 1.0 1.2
IOUT (mA)
-15
6 4 2 0 VOUT - VSS (V)
-10
-5
0 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 VOUT (V)
0 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C)
SUPPLY CURRENT vs. REFERENCE VOLTAGE
MAX509-FG03
MAX509-FG04
-40 -45 -50 THD + NOISE (dB) -55 -60 -65 -70 -75 -80 -85 -90 FREQ = 20kHz FREQ = 1kHz VDD = +5V VSS = -5V INPUT CODE = FF HEX
1%
5 4 IDD (mA) 3 2 1 0 -5 -4 -3 -2 -1 0 1 VDD = +5V ALL LOGIC INPUTS = +5V VSS = -5V
-30 THD + NOISE (dB) -40 -50 -60 -70 -80 -90
VSS = 0V
0.1%
THD + NOISE (%)
VREF = 8Vp-p 0.1% VREF = 1Vp-p VREF = 4Vp-p 10 100 1k 10k
0.01%
0.01%
2
3
4
5
0
2
4
6
8
10
100k
VREF VOLTAGE (V)
REFERENCE AMPLITUDE (Vp-p)
REFERENCE FREQUENCY (Hz)
REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE
MAX509-FG06
REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE
MAX509-FG07
REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE
0 RELATIVE OUTPUT (dB)
MAX509-FG08
0 RELATIVE OUTPUT (dB)
0 RELATIVE OUTPUT (dB)
-10
-10
-10
-20
-20
-20
-30 VDD = +5V VSS = AGND VREF = 2.5VDC + 0.5Vp-p SINE WAVE 1k 10k 100k FREQUENCY (Hz) 1M 10M
-30 VDD = +5V VSS = AGND VREF = 2.5VDC + 0.05Vp-p SINE WAVE 1k 10k 100k FREQUENCY (Hz) 1M 10M
-30 VDD = +5V VSS = -5V VREF = 2.5VDC + 4Vp-p SINE WAVE 1k 10k 100k FREQUENCY (Hz) 1M 10M
-40
-40
-40
_______________________________________________________________________________________
5
THD + NOISE (%)
VDD = +5V VSS = -5V INPUT CODE = FF HEX FREQ = SWEPT
MAX509-FG05
6
THD + NOISE AT DAC OUTPUT vs. REFERENCE AMPLITUDE
THD + NOISE AT DAC OUTPUT vs. REFERENCE FREQUENCY
-20 10%
1%
Quad, Serial 8-DACs with Rail-to-Rail Outputs MAX509/MAX510
____________________________Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
ZERO-CODE ERROR vs. NEGATIVE SUPPLY VOLTAGE
MAX509-FG09
WORST-CASE 1LSB DIGITAL STEP CHANGE
REFERENCE FEEDTHROUGH AT 40kHz
5.0 4.8 ZERO-CODE ERROR (mV) 4.6 4.4 4.2 4.0 VDD = +5V VREF = +4V
2V
20mV
A A
B
B
3.8 3.6 3.4 0 -1 -2 -3 VSS (V) -4 -5 -6
A = CS, 2V/div B = OUTA, 20mV TIMEBASE = 200ns/div
200nS
A = REFA, 10Vp-p B = OUTA, 100V/div, UNLOADED TIMEBASE = 10s/div VDD = +5V, VSS = -5V CODE = ALL 0s
REFERENCE FEEDTHROUGH AT 10kHz
REFERENCE FEEDTHROUGH AT 4kHz
REFERENCE FEEDTHROUGH AT 400Hz
5V
A
50V
A A
B
10
B
B
100S
A = REFA, 10Vp-p B = OUTA, 50V/div, UNLOADED TIMEBASE = 50s/div A = REFA, 10Vp-p B = OUTA, 50V/div, UNLOADED TIMEBASE = 100s/div A = REFA, 10Vp-p B = OUTA, 50V/div, UNLOADED TIMEBASE = 1ms/div
6
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Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs
____________________________Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
POSITIVE SETTLING TIME (VSS = AGND OR -5V)
MAX509/MAX510
CLOCK FEEDTHROUGH
5V
A
100mV
A
B
B
1S
A = SCLK, 333kHz B = OUT_, 10mV/div TIMEBASE = 2s/div A = DIGITAL INPUT, 5V/div B = OUT_ , 2V/div TIMEBASE = 1s/div VDD = +5V REF_ = +4V ALL BITS OFF TO ALL BITS ON RL = 10k, CL = 100pF
NEGATIVE SETTLING TIME (VSS = AGND)
NEGATIVE SETTLING TIME (VSS = -5V)
5V
100mV
A
5V
100mV
A
B
B
1S
A = DIGITAL INPUT, 5V/div B = OUT_ , 2V/div TIMEBASE = 1s/div VDD = +5V REF_ = +4V ALL BITS ON TO ALL BITS OFF RL = 10k, CL = 100pF A = DIGITAL INPUT, 5V/div B = OUT_ , 2V/div TIMEBASE = 1s/div VDD = +5V REF_ = +4V ALL BITS ON TO ALL BITS OFF RL = 10k, CL = 100pF
1S
_______________________________________________________________________________________
7
Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510
______________________________________________________________Pin Description
PIN MAX509 MAX510 NAME OUTB OUTA VSS REFB REFAB REFA AGND N.C. DGND LDAC DOUT CLR DAC B Voltage Output DAC A Voltage Output Negative Power Supply, 0V to -5V 10%. Connect to AGND for single-supply operation. Reference Voltage Input for DAC B Reference Voltage Input for DACs A and B Reference Voltage Input for DAC A Analog Ground Not Internally Connected Digital Ground Load DAC Input (active low). Driving this asynchronous input low (level sensitive) transfers the contents of each input latch to its respective DAC latch. Serial Data Output. Can sink and source current. Data at DOUT is adjustable to be clocked out on rising or falling edge of SCLK. Clear DAC input (active low). Driving CLR low causes an asynchronous clear of input and DAC registers and sets all DAC outputs to zero. Serial Data Input. TTL/CMOS-compatible input. Data is clocked into DIN on the rising edge of SCLK. CS must be low for data to be clocked in. Serial Clock Input. Data is clocked in on the rising edge and clocked out on either the rising (default) or the falling edge. Chip-Select Input (active low). Data is shifted in and out when CS is low. Programming commands are executed when CS rises. Reference Voltage Input for DAC D Reference Voltage Input for DACs C and D Reference Voltage Input for DAC C Positive Power Supply, +5V 10% DAC D Output Voltage DAC C Output Voltage FUNCTION
1
2 3 4 - 5 6 7, 14 8 9 10
1
2 3 - 4 - 5 - 6 7 8
11
9
12
10
DIN
13
11
SCLK
15 16 - 17 18 19 20
12 - 13 - 14 15 16
CS REFD REFCD REFC VDD OUTD OUTC
8
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Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs
_______________Detailed Description
Serial Interface
At power-on, the serial interface and all DACs are cleared and set to code zero. The serial data output (DOUT) is set to transition on SCLK's rising edge. The MAX509/MAX510 communicate with microprocessors through a synchronous, full-duplex, 3-wire interface (Figure 1). Data is sent MSB first and can be transmitted in one 4-bit and one 8-bit (byte) packet or in one 12-bit word. If a 16-bit control word is used, the first four bits are ignored. A 4-wire interface adds a line for LDAC and allows asynchronous updating. The serial clock (SCLK) synchronizes the data transfer. Data is transmitted and received simultaneously. Figure 2 shows a detailed serial interface timing. Please note that the clock should be low if it is stopped
MAX509/MAX510
between updates. DOUT does not go into a highimpedance state if the clock or CS is high. Serial data is clocked into the data registers in MSBfirst format, with the address and configuration information preceding the actual DAC data. Data is clocked in on SCLK's rising edge while CS is low. Data at DOUT is clocked out 12 clock cycles later, either at SCLK's rising edge (default or mode 1) or falling edge (mode 0). Chip select (CS) must be low to enable the DAC. If CS is high, the interface is disabled and DOUT remains unchanged. CS must go low at least 40ns before the first rising edge of the clock pulse to properly clock in the first bit. With CS low, data is clocked into the MAX509/MAX510's internal shift register on the rising edge of the external serial clock. SCLK can be driven at rates up to 12.5MHz.
INSTRUCTION EXECUTED CS
*** ***
SCLK
DIN A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 MSB DACA DOUT MODE 1 (DEFAULT) LSB A1
***
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 MSB DACD D1 D0 LSB A1
***
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1
DATA FROM PREVIOUS DATA INPUT
DATA FROM PREVIOUS DATA INPUT
DOUT MODE 0 A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1
***
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1
Figure 1. MAX509/MAX510 3-Wire Interface Timing
_______________________________________________________________________________________
9
Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510
tCLL CS
***
tCSH2
tCSS tCSH0
tCH
***
SCLK tDS tDH
***
tCL
tCSH1
DIN tDO
***
DOUT
***
LDAC
NOTE: TIMING SPECIFICATION tCLL IS RECOMMENDED TO MINIMIZE OUTPUT GLITCH, BUT IS NOT MANDATORY.
tLDW
Figure 2. Detailed Serial Interface Timing (Mode 0 Shown)
Table 1. Serial-Interface Programming Commands
12-Bit Serial Word A1 0 0 1 1 0 0 1 1 X X 0 A0 0 1 0 1 0 1 0 1 0 1 X C1 0 0 0 0 1 1 1 1 0 0 1 C0 1 1 1 1 1 1 1 1 0 0 0 D7 . . . . . . . . D0 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data XXXXXXXX XXXXXXXX LDAC 1 1 1 1 1 1 1 1 X X X Function Load DAC A input register, DAC output unchanged. Load DAC B input register, DAC output unchanged. Load DAC C input register, DAC output unchanged. Load DAC D input register, DAC output unchanged. Load input and DAC register A. Load input and DAC register B. Load input and DAC register C. Load input and DAC register D. Update all DACs from shift register. No Operation (NOP), shifts data in shift register. "LDAC" Command, all DACs updated from respective input registers. Mode 1, DOUT clocked out on rising edge of SCLK (default). All DACs updated from respective input registers. Mode 0, DOUT clocked out on falling edge of SCLK. All DACs updated from input registers.
1
1
1
0
XXXXXXXX
X
1
0
1
0
XXXXXXXX
X
10
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Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs
Serial Input Data Format and Control Codes The 12-bit serial input format shown in Figure 3 comprises two DAC address bits (A1, A0), two control bits (C1, C0) and eight bits of data (D0...D7). The 4-bit address/control code configures the DAC as shown in Table 1.
This is the first bit shifted in
MSB DOUT A1 A0C1 C0 D7D6
qqq
Update All DACs from Shift Registers
A1 x A0 0 C1 0 C0 0 D7 D6 D5 D4 D3 D2 D1 D0 8-Bit DAC Data
MAX509/MAX510
(LDAC = x)
LSB D1 D0 DIN
All four DAC registers are updated with shift-register data. This command allows all DACs to be set to any analog value within the reference range. This command can be used to substitute CLR if code 00 hex is programmed, which clears all DACs.
Control and Address bits
Figure 3. Serial Input Format
8-bit DAC data
A1 x A0 1 C1 0 C0 0 D7 x D6 x D5 x
No Operation (NOP)
D4 x D3 x D2 x D1 x D0 x
(LDAC = x)
Load Input Register, DAC Registers Unchanged (Single Update Operation)
A1 A0 Address (LDAC = H) C1 0 C0 1 D7 D6 D5 D4 D3 D2 D1 D0 8-Bit Data
When performing a single update operation, A1 and A0 select the respective input register. At the rising edge of CS, the selected input register is loaded with the current shift-register data. All DAC outputs remain unchanged. This preloads individual data in the input register without changing the DAC outputs.
The NOP command (no operation) allows data to be shifted through the MAX509/MAX510 shift register without affecting the input or DAC registers. This is useful in daisy chaining (also see the Daisy-Chaining Devices section). For this command, the data bits are "Don't Cares." As an example, three MAX509/MAX510s are daisy-chained (A, B and C), and DAC A and DAC C need to be updated. The 36-bit-wide command would consist of one 12-bit word for device C, followed by an NOP instruction for device B and a third 12-bit word with data for device A. At CS's rising edge, only device B is not updated.
"LDAC" Command (Software)
A1 0 A0 x C1 1 C0 0 D7 x D6 x D5 x D4 x D3 x D2 x D1 x D0 x
Load Input and DAC Registers
A1 A0 Address (LDAC = H) C1 1 C0 1 D7 D6 D5 D4 D3 D2 8-Bit Data D1 D0
(LDAC = x)
This command directly loads the selected DAC register at CS's rising edge. A1 and A0 set the DAC address. Current shift-register data is placed in the selected input and DAC registers. For example, to load all four DAC registers simultaneously with individual settings (DAC A = 1V, DAC B = 2V, DAC C = 3V and DAC D = 4V), five commands are required. First, perform four single input register update operations. Next, perform an "LDAC" command as a fifth command. All DACs will be updated from their respective input registers at the rising edge of CS.
All DAC registers are updated with the contents of their respective input registers at CS's rising edge. With the exception of using CS to execute, this performs the same function as the asynchronous LDAC.
Set DOUT Phase - SCLK Rising (Mode 1, Default)
A1 1 A0 1 C1 1 C0 0 D7 x D6 x D5 x D4 x D3 x D2 x D1 x D0 x
(LDAC = x)
Mode 1 resets the serial output DOUT to transition at SCLK's rising edge. This is the MAX509/MAX510's default setting after the supply voltage has been applied. The command also loads all DAC registers with the contents of their respective input registers, and is identical to the "LDAC" command.
11
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Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510
Set DOUT Phase - SCLK Falling (Mode 0)
A1 1 A0 0 C1 1 C0 0 D7 x D6 x D5 x D4 x D3 x D2 x D1 x D0 x
SCLK SK SO SI I/0 MICROWIRE PORT
(LDAC = x)
MAX509 DIN MAX510
DOUT CS
This command resets DOUT to transition at SCLK's falling edge. Once this command is issued, the phase of DOUT is latched and will not change except on power-up or if the specific command is issued that sets the phase to rising edge. The same command also updates all DAC registers with the contents of their respective input registers, identical to the "LDAC" command.
THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX509/MAX510, BUT MAY BE USED FOR READ-BACK PURPOSES.
Figure 4. Connections for Microwire
LDAC Operation (Hardware) LDAC is typically used in 4-wire interfaces (Figure 7). LDAC allows asynchronous hardware control of the DAC outputs and is level-sensitive. With LDAC low, the DAC registers are transparent and any time an input register is updated, the DAC output immediately follows. Clear DACs with CLR Strobing the CLR pin low causes an asynchronous clear of input and DAC registers and sets all DAC outputs to zero. Similar to the LDAC pin, CLR can be invoked at any time, typically when the device is not selected (CS = H). When the DAC data is all zeros, this function is equivalent to the "Update all DACs from Shift Registers" command. Digital Inputs and Outputs Digital inputs and outputs are compatible with both TTL and 5V CMOS logic. The power-supply current (IDD) depends on the input logic levels. Using CMOS logic to drive CS, SCLK, DIN, CLR and LDAC turns off the internal level translators and minimizes supply currents. Serial Data Output DOUT is the output of the internal shift register. DOUT can be programmed to clock out data on SCLK's falling edge (mode 0) or rising edge (mode 1). In mode 0, output data lags the input data by 12.5 clock cycles, maintaining compatibility with Microwire, SPI, and QSPI. In mode 1, output data lags the input by 12 clock cycles. On power-up, DOUT defaults to mode 1 timing. DOUT never three-states; it always actively drives either high or low and remains unchanged when CS is high. Interfacing to the Microprocessor The MAX509/MAX510 are Microwire, SPI, and QSPI compatible. For SPI and QSPI, clear the CPOL and CPHA configuration bits (CPOL = CPHA = 0). The SPI/QSPI CPOL = CPHA = 1 configuration can also be used if the DOUT output is ignored.
DOUT
MISO MOSI SCK I/0
MAX509 DIN MAX510
SCLK CS
SPI PORT
CPOL = 0, CPHA = 0 THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX509/MAX510, BUT MAY BE USED FOR READ-BACK PURPOSES.
Figure 5. Connections for SPI
The MAX509/MAX510 can interface with Intel's 80C5X/80C3X family in mode 0 if the SCLK clock polarity is inverted. More universally, if a serial port is not available, three lines from one of the parallel ports can be used for bit manipulation. Digital feedthrough at the voltage outputs is greatly minimized by operating the serial clock only to update the registers. Also see the Clock Feedthrough photo in the Typical Operating Characteristics section. The clock idle state is low.
Daisy-Chaining Devices Any number of MAX509/MAX510s can be daisy-chained by connecting the DOUT pin of one device to the DIN pin of the following device in the chain. The NOP instruction (Table 1) allows data to be passed from DIN to DOUT without changing the input or DAC registers of the passing device. A threewire interface updates daisy-chained or individual MAX509/MAX510s simultaneously by bringing CS high.
12
______________________________________________________________________________________
Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510
MAX509
SCLK DIN CS SCLK MAX510 DIN CS DOUT
MAX509
SCLK MAX510 DIN CS DOUT
MAX509
SCLK MAX510 DIN CS TO OTHER SERIAL DEVICES DOUT
SCLK DIN CS
SCLK MAX510 DIN CS
MAX509
Figure 6. Daisy-chained or individual MAX509/MAX510s are simultaneously updated by bringing CS high. Only three wires are required.
DIN SCLK LDAC CS1 CS2 CS3 TO OTHER SERIAL DEVICES
CS LDAC MAX509
CS LDAC MAX509
CS LDAC MAX509
MAX510
SCLK DIN SCLK DIN
MAX510
SCLK DIN
MAX510
Figure 7. Multiple MAX509/MAX510 DACs sharing one DIN line. Simultaneously update by strobing LDAC, or specifically update by enabling individual CS.
______________________________________________________________________________________ 13
Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510
dependent: 15pF typical for the MAX509 and 30pF typical for the MAX510. The output voltage for any DAC can be represented by a digitally programmable voltage source as: VOUT = (NB x VREF) / 256 where NB is the numerical value of the DAC's binary input code.
R
R 2R D5 2R D6
R 2R D7
OUT_
2R
2R D0
REF_ AGND SHOWN FOR ALL 1 ON DAC
Figure 8. DAC Simplified Circuit Diagram
If multiple devices share a common DIN line, Figure 7's configuration provides simultaneous update by strobing LDAC low. CS1, CS2, CS3... are driven separately, thus controlling which data are written to devices 1, 2, 3....
Output Buffer Amplifiers All MAX509/MAX510 voltage outputs are internally buffered by precision unity-gain followers that slew at up to 1V/s. The outputs can swing from VSS to VDD. With a 0V to +4V (or +4V to 0V) output transition, the amplifier outputs will settle to 1/2LSB in typically 6s when loaded with 10k in parallel with 100pF. The buffer amplifiers are stable with any combination of resistive loads 2k and capacitive loads 300pF.
__________Applications Information
Power Supply and Reference Operating Ranges
The MAX509/MAX510 are fully specified to operate with VDD = 5V 10% and VSS = 0V to -5.5V. 8-bit performance is guaranteed for both single- and dual-supply operation. The zero-code output error is less than 14mV when operating from a single +5V supply. The DACs work well with reference voltages from VSS to VDD. The reference voltage is referred to AGND. The preferred power-up sequence is to apply VSS and then VDD, but bringing up both supplies at the same time is also acceptable. In either case, the voltage applied to REF should not exceed VDD during powerup or at any other time. If proper power sequencing is not possible, connect an external Schottky diode between VSS and AGND to ensure compliance with the Absolute Maximum Ratings. Do not apply signals to the digital inputs before the device is fully powered up.
Analog Section
DAC Operation The MAX509/MAX510 contain four matched voltageoutput DACs. The DACs are inverted R-2R ladder networks that convert 8-bit digital words into equivalent analog output voltages in proportion to the applied reference voltages. Each DAC in the MAX509 has a separate reference input, while the two reference inputs in the MAX510 each share a pair of DACs. The two reference inputs permit different full-scale output voltage ranges for each pair of DACs. A simplified diagram of one of the four DACs is shown in Figure 8. Reference Input The MAX509/MAX510 can be used for multiplying applications. The reference accepts both DC and AC signals. The voltage at each REF input sets the fullscale output voltage for its respective DAC(s). If the reference voltage is positive, both the MAX509 and MAX510 can be operated from a single supply. If dual supplies are used, the reference input can vary from VSS to VDD, but is always referred to AGND. The input impedance at REF is code dependent, with the lowest value (16k for the MAX509 and 8k for the MAX510) occurring when the input code is 55 hex or 0101 0101. The maximum value, practically infinity, occurs when the input code is 00 hex. Since the REF input impedance is code dependent, the DAC's reference sources must have a low output impedance (no more than 32 for the MAX509 and 16 for the MAX510) to maintain output linearity. The REF input capacitance is also code
14
Power-Supply Bypassing and Ground Management
In single-supply operation (AGND = DGND = VSS = 0V), AGND, DGND and V SS should be connected together in a "star" ground at the chip. This ground should then return to the highest quality ground available. Bypass VDD with a 0.1F capacitor, located as close to VDD and DGND as possible. In dual-supply operation, bypass VSS to AGND with 0.1F. Careful PC board layout minimizes crosstalk among DAC outputs, reference inputs, and digital inputs. Figures 9 and 10 show suggested circuit board layouts to minimize crosstalk.
______________________________________________________________________________________
Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510
SYSTEM GND SYSTEM GND OUTC OUTD VDD REFC REFD OUTB OUTA VSS REFB REFA AGND OUTC OUTD VDD REFCD OUTB OUTA VSS REFAB AGND
Figure 9. Suggested MAX509 PC Board Layout for Minimizing Crosstalk (Bottom View)
Figure 10. Suggested MAX510 PC Board Layout for Minimizing Crosstalk (Bottom View)
Unipolar-Output, 2-Quadrant Multiplication
In unipolar operation, the output voltages and the reference input(s) are the same polarity. Figures 11 and 12 show the MAX509/MAX510 unipolar configurations. Both devices can be operated from a single supply if the reference inputs are positive. If dual supplies are used, the reference input can vary from VSS to VDD. Table 2 shows the unipolar code.
Bipolar-Output, 2-Quadrant Multiplication
Bipolar-output, 2-quadrant multiplication is achieved by offsetting AGND positively or negatively. Table 3 shows the bipolar code. AGND can be biased above DGND to provide an arbitrary nonzero output voltage for a 0 input code, as shown in Figure 13. The output voltage at OUTA is: VOUTA = VBIAS + (NB/256)(VIN),
Table 2. Unipolar Code Table
DAC CONTENTS MSB 1111 LSB 1111 ANALOG OUTPUT +VREF 255 256 +VREF 129 256 +VREF
Table 3. Bipolar Code Table
DAC CONTENTS MSB 1111 LSB 1111 ANALOG OUTPUT +VREF 127 128 +VREF
(----)
(----)
1 (----) 128
1000
0001
(----)
V
1000 1000 0111
0001 0000 1111
1000
0000
REF 128 (----) = + ---- 256 2
0V -VREF -VREF 1 (----) 128 127 (----) 128
0111
1111
+VREF
(----) 256
0000 0001
127
0000 0000
0001 0000
1 +VREF 256 0V
(----)
0000 0000
-VREF 128 128
(----) = -VREF
1 Note: 1LSB = (VREF) (2-8) = +VREF (----) 256
______________________________________________________________________________________ 15
Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510
REFERENCE INPUTS (VSS TO VDD) 5 4 17 16 REFA REFB REFC REFD +5V 18 VDD 2 DAC A +5V 5 REFA OUTA 2 VIN 1 DAC B SERIAL INTERFACE NOT SHOWN 20 DAC C OUTC OUTB VBIAS 6 AGND DAC A OUTA 18 VDD
MAX509
VSS 3 -5V (OR GND) +5V 4 REFAB 14 VDD DGND 8
19 DAC D DGND 8 OUTD AGND 6
VSS 3
2 VIN 5 AGND DAC A
OUTA
MAX509
-5V (OR GND)
Figure 11. MAX509 Unipolar Output Circuit
MAX510
VBIAS VSS 3 -5V (OR GND) DGND 6
REFERENCE INPUTS (VSS TO VDD) 4 REFAB
+5V 14 VDD 2
SERIAL INTERFACE NOT SHOWN
DAC A
OUTA
Figure 13. MAX509/MAX510 AGND Bias Circuits (Positive Offset)
1 DAC B SERIAL INTERFACE NOT SHOWN 16 DAC C OUTC OUTB
15 DAC D DGND 6 OUTD AGND 5
VSS 3
REFCD 13
-5V (OR GND)
MAX510
Figure 12. MAX510 Unipolar Output Circuit
where NB represents the digital input word. Since AGND is common to all four DACs, all outputs will be offset by VBIAS in the same manner. Do not bias AGND more than +1V above DGND, or more than 2.5V below DGND. Figures 14 and 15 illustrate the generation of negative offsets with bipolar outputs. In these circuits, AGND is biased negatively (up to -2.5V with respect to DGND) to provide an arbitrary negative output voltage for a 0 input code. The output voltage at OUTA is: OUTA = -(R2/R1)(2.5V) + (NB/256)(2.5V)(R2/R1+1) where NB represents the digital input word. Since AGND is common to all four DACs, all outputs will be offset by V BIAS in the same manner. Table 3, with VREF = 2.5V, shows the digital code vs. output voltage for Figure 14 and 15's circuits with R1 = R2. The ICL7612 op amp is chosen because its common-mode range extends to both supply rails.
16
______________________________________________________________________________________
Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510
REFERENCE INPUTS +5V 0.1F
5 +5V SERIAL INTERFACE NOT SHOWN 0.1F
4
17
16
18 VDD
MAX509
2 DAC A OUTA
MAX873
+2.5V
R1 330k 0.1%
R2 330k 0.1% DAC B +5V 0.1F 2 3 7 6 8 DAC D 0.1F VSS -5V 0.1F -5V 3 AGND 6 DGND 8
1
OUTB
DAC C
20
OUTC
19 OUTD
ICL7611A
1
Figure 14. MAX509 AGND Bias Circuit (Negative Offset)
4-Quadrant Multiplication
Each DAC output may be configured for 4-quadrant multiplication using Figure 16 and 17's circuit. One op amp and two resistors are required per channel. With R1 = R2: VOUT = VREF [2(NB/256)-1] where NB represents the digital word in DAC register A. The recommended value for resistors R1 and R2 is 330k (0.1%). Table 3 shows the digital code vs. output voltage for Figure 16 and 17's circuit.
______________________________________________________________________________________
17
Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510
REFERENCE INPUTS +5V SERIAL INTERFACE NOT SHOWN R1 330k 0.1% +2.5V +5V 0.1F 2 3 7 6 8 DAC D 0.1F VSS -5V 0.1F -5V 3 AGND 5 DGND 6 15 1 OUTD 16 R2 330k 0.1% DAC B 4 13 +5V 14 VDD 0.1F 2 0.1F
MAX510
DAC A 2 OUTA
MAX873
4
6
1
OUTB
DAC C
OUTC
ICL7611A
Figure 15. MAX510 AGND Bias Circuit (Negative Offset)
REFERENCE INPUTS (VSS TO VDD)
+5V 0.1F 0.1F R1 R2
5
4
17
16
+5V 18 VDD
MAX509
DAC A 2 OUTA
ICL7612A*
VOUT
0.1F SERIAL INTERFACE NOT SHOWN 1 DAC B OUTB 0.1F DAC C 20 OUTC 19 OUTD VSS 3 0.1F *CONNECT ICL7612A PIN 8 TO AGND AGND OR -5V AGND 6 DGND 8 0.1F -5V R1 R2 +5V -5V
ICL7612A*
DAC D
VOUT
Figure 16. MAX509 Bipolar Output Circuit
18 ______________________________________________________________________________________
Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510
REFERENCE INPUTS +5V 4 13 +5V 14 VDD 0.1F 0.1F R1
MAX510
2 DAC A OUTA
R2
ICL7612A*
VOUT
0.1F SERIAL INTERFACE NOT SHOWN 1 DAC B OUTB -5V +5V 0.1F R1 R2 15 DAC D OUTD VSS 3 0.1F AGND OR -5V *CONNECT ICL7612A PIN 8 TO AGND AGND 5 DGND 6 0.1F -5V
DAC C
16 OUTC
ICL7612A*
VOUT
Figure 17. MAX510 Bipolar Output Circuit
__Functional Diagrams (continued)
DOUT CLR LDAC AGND DGND VSS VDD REFB DECODE CONTROL REFA
____Pin Configurations (continued)
TOP VIEW
OUTA
MAX509
INPUT REG A DAC REG A OUTB 1 OUTA 2 V SS 3 OUTB 16 OUTC 15 OUTD 14 V DD DAC A
12-BIT SHIFT REGISTER
INPUT REG B
DAC REG B
REFAB 4 AGND 5 DGND 6
MAX510
13 REFCD 12 CS 11 SCLK 10 DIN 9 CLR
DAC B
OUTC INPUT REG C DAC REG C DAC C
LDAC 7 DOUT 8
OUTD SR CONTROL INPUT REG D DAC REG D DAC D
DIP/Wide SO
CS DIN SCLK
REFC
REFD
______________________________________________________________________________________
19
Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510
_Ordering Information (continued)
PART MAX509AEPP MAX509BEPP MAX509AEWP MAX509BEWP MAX509AEAP MAX509BEAP MAX509AMJP MAX509BMJP MAX510ACPE TEMP. RANGE -40C to +85C PIN-PACKAGE 20 Plastic DIP TUE (LSB) 1
REFB (REFAB)
___________________Chip Topography
MAX509/MAX510
V SS OUTA OUTB OUTC OUTD V DD REFC (REFCD) REFD (REFCD) CS REFA (REFAB) AGND 0.121" (3.07mm)
-40C to +85C 20 Plastic DIP 1 1/2 -40C to +85C 20 Wide SO 1 -40C to +85C 20 Wide SO 1 1/2 -40C to +85C 20 SSOP 1 -40C to +85C 20 SSOP 1 1/2 -55C to +125C 20 CERDIP** 1 -55C to +125C 20 CERDIP** 1 1/2 0C to +70C 16 Plastic DIP 1 MAX510BCPE 0C to +70C 16 Plastic DIP 1 1/2 MAX510ACWE 0C to +70C 16 Wide SO 1 MAX510BCWE 0C to +70C 16 Wide SO 1 1/2 MAX510AEPE -40C to +85C 16 Plastic DIP 1 MAX510BEPE -40C to +85C 16 Plastic DIP 1 1/2 MAX510AEWE -40C to +85C 16 Wide SO 1 MAX510BEWE -40C to +85C 16 Wide SO 1 1/2 MAX510AMJE -55C to +125C 16 CERDIP** 1 MAX510BMJE -55C to +125C 16 CERDIP** 1 1/2 **Contact factory for availability and processing to MIL-STD-883.
DGND LDAC DOUT CLR 0.128" (3.25mm) DIN
SCLK
NOTE: LABELS IN ( ) ARE FOR MAX510 ONLY. TRANSISTOR COUNT: 2235; SUBSTRATE CONNECTED TO VDD.
________________________________________________________Package Information
DIM INCHES MAX MIN 0.078 0.068 0.008 0.002 0.015 0.010 0.009 0.005 0.289 0.278 0.212 0.205 0.0256 BSC 0.311 0.301 0.037 0.022 8 0 MILLIMETERS MIN MAX 1.73 1.99 0.05 0.21 0.25 0.38 0.13 0.22 7.07 7.33 5.20 5.38 0.65 BSC 7.65 7.90 0.55 0.95 0 8
21-0003A
e
E
H
A A1 B C D E e H L
D A
0.127mm 0.004in.
B
A1
C
L
20-PIN PLASTIC SHRINK SMALL-OUTLINE PACKAGE
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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